1. Field of the Invention
The present invention relates to a thin film transistor (TFT) substrate, an electronic apparatus, and methods for fabricating the same and, more particularly, relates to a TFT substrate in which a channel region has sub-grain boundaries and relates to an arrangement of the sub-grain boundaries, an electronic apparatus, and methods for fabricating the same.
2. Description of Related Art
Recently, with an advancement of optoelectronic technologies and semiconductor fabricating technologies, a flat panel displays have been vigorously developed. Among the flat panel displays, a liquid crystal displays (LCDs) characterized by low operating voltage, no harmful radiation, light weight, and compactness have gradually replaced conventional CRT displays and become mainstream display products.
In general, the LCD can be categorized into an amorphous silicon TFT-LCD and a low temperature polysilicon TFT-LCD. Compared with the amorphous silicon TFT, the low temperature polysilicon TFT has a relatively high electron mobility (by two to three orders of magnitude, and therefore the polysilicon TFT not only can serve as a switch of a pixel, but also can be applied in peripheral circuit regions as a circuit for driving the LCD.
Practically, the TFT acting as the switch of the pixel and the TFT acting as the driving circuit require different properties. The TFT serving as the switch of the pixel is normally required to achieve high uniformity of electrical characteristics, while the TFT acting as the driving circuit should be characterized by high mobility of carriers and high electrical reliability. Here, device characteristics of the TFT are closely associated with crystallization forms and crystallization locations in the polysilicon layer. In particular, electrical performance of the TFT mainly results from the crystallization form of the polysilicon layer in a channel region.
FIG. 1 is a schematic view of a conventional sequential lateral solidification (SLS) laser crystallization apparatus 100 for forming polysilicon. Please refer to FIG. 1, the SLS laser crystallization apparatus 100 includes a laser source (not shown), an optical system 110, and a substrate carrier 120, wherein the optical system 110 has a mask 112, and a modulator 114. The SLS laser crystallization apparatus 100 is an improvement of an excimer laser crystallization apparatus. Specifically, the highly-precise optical system 110 and the substrate carrier 120 capable of being moved within a sub-micro range for carrying a substrate 130 are additionally installed in the original excimer laser system.
FIG. 2A is a schematic view of a conventional SLS laser crystallization apparatus in which crystallization is being performed on a polysilicon layer. FIG. 2B is a schematic top view of the polysilicon layer fabricated by performing the crystallization as shown in FIG. 2A. Referring to FIG. 2A, through a mask design of a mask 112, laser beams penetrating slits S of the mask 112 are patterned and then emitted to an amorphous silicon layer 140 (α-Si shown in FIG. 1) on the substrate 130 via the modulator 114. Thereafter, referring to FIG. 2B, a polysilicon layer 150 (p-Si shown in FIG. 1) having a structure of periodic grain boundaries is formed by controlling regions of film sequential lateral solidification and grain boundary locations through the pattern design of the mask depicted in FIG. 2A. Here, the polysilicon layer 150 includes main grain boundaries (MGBs) and sub-grain boundaries (SGBs).
In general, the SGBs are often parallel to grain growing directions, while the MGBs are substantially perpendicular to the SGBs. Hence, when a line connecting the centroid of a source region with the centroid of a drain region is parallel to the SGBs, the carrier mobility in the channel region is improved. On the contrary, when the line connecting the centroid of the source region with the centroid of the drain region is parallel to the MGBs, the carriers are prone to be trapped in the SGBs, such that the carrier mobility in the channel region is reduced. In other words, the carrier mobility in the channel region is profoundly affected by the orientation of the MGBs and SGBs in the polysilicon layer having a highly anisotropic crystallization form.
However, to meet actual demands on partial layout of the TFT array substrate, the TFTs placed in various locations on the TFT array substrate may have the channel regions in different directions. For instance, the TFT disposed in a peripheral circuit region may have a different channel direction from that of the TFT disposed in a display region. In detail, the demand on layout of some of the TFTs disposed in the display region lies in that the directions of the channel regions in the TFTs are parallel to the MGBs of the polysilicon, while the demand on the layout of some of the TFTs disposed in the peripheral circuit region rests in that the directions of the channel regions in the TFTs are parallel to the SGBs of the polysilicon. Since the carrier mobility in the channel region is closely related to the crystallization form of the polysilicon, the anisotropic property of the polysilicon leads to variations in characteristics of the TFTs on the TFT array substrate, thereby deteriorating uniformity of electrical characteristics of the TFTs. As such, mura effects may be generated, and display quality is reduced.